Don’t give up Rowan, I’m sure that this can be done with that IC… Flownez and I discussed it at length this weekend, in fact he pointed out that if you didn’t nheed MIDI control you wouldn’t even need MIOS, you could just run the thing through a serial port…
Anyway I want MIDI control and I’m keen to do this, the cheap way with the IC…
I guess the real problem is that I don’t have heaps of time on my hands, I work pretty long hours… I know this is a university program for you so it’s not something that you can just do “whenever”… However I won’t be doing much more work on the sequencer until TK releases the 18F port of the MB64Seq, so maybe between the three of us…?
What’s your timeframe look like?
Anyway as for clocking… now before I open my big mouth I’d like to reinstate my previous comments about how I’m sh*t with electronics 
According to the datasheet:
The serial shift register is dynamic, so there is a minimum clock rate of 20 kHz. The maximum clock
rate of 5 MHz allows loading times as short as 52 ms.
From that statement and the other nerdy stuff on that doc, I’ve gathered that basically you push data to control the switches into the serial in, and push it a clock signal after whenever the serial data for each switch is loaded. This shifts the data to the next register… Once all the required registers are full (you’ve finished sending it data about how to configure the switch), you send it a PCLK pulse and that moves all the data about how to set the 256 switches, into the chip and moves the switches accordingly…
Provided of course that the data you push into it doesn’t clock below 20khz which is the minimum clock speed…
I should have read this datasheet closer before 
So the MIOS side of it will need three digital outs… One to push data to the chip which represents the state of the switches. One to push a clock signal to lock those bits in place. And one to send the parallel clock signal to tell the chip ‘OK go load this stuff into the switches and patch this sucker already’…
Food for thought? Geez I hope I got this techy crud right or I’ll look like a right dork!
Anyway here’s the juicey bit from the datasheet:
APPLICATIONS INFORMATION
Loading Data
Data to control the switches is clocked serially into a 256-bit shift register and then transferred in parallel to 256 bits of mem-ory. The rising edge of SCLK, the serial clock input, loads data into the shift register. The first bit loaded via SIN, the serial data input, controls the switch at the intersection of row Y15 and column X15. The next bits control the remaining columns (down to X0) of row Y15, and are followed by the bits for row Y14, and so on down to the data for the switch at the intersec-tion of row Y0 and column X0. The shift register is dynamic, so there is a minimum clock rate, specified as 20 kHz. After the shift register is filled with the new 256 bits of control data, PCLK is activated (pulsed low) to transfer the data to the parallel latches. Since the shift register is dynamic, there is a maximum time delay specified before the data is lost: PCLK must be activated and brought back high within 5 ms after fill-ing
the shift register. The switch control latches are static and will hold their data as long as power is applied.
To extend the number of switches in the array, you may cascade multiple AD75019s. The SOUT output is the end of the shift register, and may be directly connected to the SIN input of the next AD75019.