2A03 internal hardware port map
The sound hardware internal to the 2A03 has been designated these special memory addresses in the 6502’s memory map.
$4000-$4003 Rectangle wave 1 (The bits between, are for chanching the sound…)
$4004-$4007 Rectangle wave 2 (nearly identical to first)
$4008-$400B Triangle
$400C-$400F Noise
$4010 DMC play mode and DMA frequency
$4011 DMC delta counter
$4012 DMC play code’s starting address
$4013 DMC length of play code
$4014 transfer 256 bytes from written page to $2004
$4015r Channel enable / length/frame counter status
$4017 frame counter control
Note: $4015 is the only R/W register here. All others do not respond to read
cycles. Reads from $4016 and $4017 are decoded inside the 2A03, and those
signals are available externally. Writes to bits D0-D2 of $4016 updates an
internal 3-bit latch, with the status of those bits available externally.
e.g.:
±-------------+
|Register set 1|
±-------------+
$4000(rct1)/$4004(rct2)/$400C(noise) bits
0-3 volume / envelope decay rate
4 envelope decay disable
5 length counter clock disable / envelope decay looping enable
6-7 duty cycle type (unused on noise channel)
all instructions where any $nn,X and $nnnn,X addressing mode rows intersect
with opcode columns 82 and A2, use the Y register for indexing
*2A03 pinings*
The net is full with this information (above) but nobody can tell me on witch input i should send this information.
I think about on data bus D0 -D7 the d0 - D-7 are going directly to the programm rom of the catrige> i hang 
___ ___
|* / |
ROUT <01] [40< VCC
COUT <02] [39> $4016W.0
/RES >03] [38> $4016W.1
A0 <04] [37> $4016W.2
A1 <05] [36> /$4016R
A2 <06] [35> /$4017R
A3 <07] [34> R/W
A4 <08] [33< /NMI
A5 <09] [32< /IRQ
A6 <10] 2A03 [31> PHI2
A7 <11] [30< —
A8 <12] [29< CLK
A9 <13] [28] D0
A10 <14] [27] D1
A11 <15] [26] D2
A12 <16] [25] D3
A13 <17] [24] D4
A14 <18] [23] D5
A15 <19] [22] D6
VEE >20] [21] D7
|________|
ROUT: audio out -> rectangle wave out
COUT: audio out -> triangle + noise
/RES: hard reset on zero (conect to ground, when want to reset?)
A0-A15: the 6502’s address bus output pins.
VEE, VCC: Power -> ground + +5VDC
D0-D7: the 6502’s data bus.
CLK: Masterclock input line (236250/11 KHz)
—: wire to ground -> unknown functionality
PHI2: Divedet by 12 Clock 1.79 MHz output.
/IRQ: interrupts the 6502 when this pin is set to zero while the 6502’s
internal interrupt mask flag is 0.
/NMI: NMI’s the 6502 on a negative edge signal transition (1->0).
R/W: direction of 6502’s data bus (0=write;1=read).
/$4017R: goes active (zero) when A0-A15 = $4017, R/W = 0, and PHI2 = 1.
This informs an external 3-state inverter to throw controller port data onto the
D0-D7 lines.
/$4016R: goes active (zero) when A0-A15 = $4016, R/W = 0, and PHI2 = 1.
$4016W.0, $4016W.1, $4016W.2: these signals represent the real-time status
of a 3 bit writable register located at $4016 in the 6502 memory map. In
NES/FC consoles, $4016W.0 is used as a strobe line for the CMOS 4021 shift
register used inside NES/FC controllers
