Hi.
I feared that this situation should occur! I will try to be pedagogic about it!
I have 20+ years of electronic enginering, i have designed many embeedded systems,
very high speed optical transmission system 900Mhz up to 8Ghz, real time ASIC
emulators at very high speed, huge amount of analog signal processing devices.
I have once been working at R/D at one of the largest mobile companies around
as a design engineer and as a PCB engineer doing mixed LF,RF and power RF
design.
I have been there, see it, done it, (typical engineer slogan) im not a super
engineer , im not even a engineer, and i dont even pretend to be one,
however, i do think i know what im talking about, you simply dont do
what you suggest, its simply not an adequate design procedure.
>there are very obvious reasons why I left out the bypass caps on most modules:
>I was forced to limit the PCB area so that it fits with a euro size board. This was due
>to Eagle freeware license limitations (e.g., it isn’t possible to create a board which is
>larger than 100 mm), and due to the yield (number of modules which can be made
>from one euroboard) which was a requirement from Mike to keep the costs low.
>I think that SmashTV has the same requirements - please correct me if I’m wrong!
If thats the reason, then it was a bad design desicion!
Sorry, but not a good excuse im afarid!
>So, my idea was, if additional caps are really required,
>then they could be mounted at the bottom of the PCB.
Its not if they are really required, they are ALWAYS required,period!
And yes mount it on the bottom side SMD or trough hole dosent matter
as long as there is any.
>Since MBHP will never go into a professional production, where manual
>effort counts, I thought that this would be an adequate solution.
It has nothing to do with professional production or if its going
to be a home DIY, its completely irrelevant. Se above statement.
>But then I did some experiments with chained DINX4 and DOUTX4 modules
>and noticed no problems even without caps - also no “beta tester” reported
>problems - so I left them out from the schematics
>(my general worldly wisdom: so long nobody proves the converse, I don’t believe it ;-
And boy, what you will fool your self by making that statement, im sorry Torsten
but that simply show your lack of experience by making that kind of statements.
You are an exellent software writer but you are “not” a hardware designer.
Not yet anyway!
>I learned in university that bypass caps are required to store and release
>energy on high current peaks.
Universityes today are miss leading the students, store and release energy
is for POWER applications, this is a HF to RF design, low current, fast rise
and fall times, over tones, resonance, impedance planes,bounching.
In uni you will only learn the thin surface, in real life it takes time to understand
things in depth, it takes years to become a quality engineer even the most trivial
tasks can if circumstances are right wreck a entire design, i have sen it,
i have even done it once! 
No one is without faults!
Here is a short story of life!
I and work mate once worked as test engineers, we did the final test
(burn in and compliance tests) for the first GSM base stations on the
market, (1990) we where quite stunned when in cabinet after cabinet,
every high speed DSP memory fused with a loud bang and flew around
inside the 2meters cabinets propelled by the rack fan blades!
We had to take cover!
There was 3 memories for each DSP, 6 DSP’s on each card,
12 cards in each rack, and 3 rack in every cabinet.(as far i can recall it).
What was the cause to this extrodinary violence??
The software engineers had ignored the hardware engineers design note
and runned the DSPs memory busses to fast, the memories behaved
in that they clocked all right but because of the speed it vent over the
ICs power dissipation limit and fused/blow!
The software enginers lowered the memory access speed and
everything was fine!
I could tell you many more interesting stories what hapends
at the big corporations when one dont follow given design roules!
As the story when i was the hardware engineer and the assembly techican
ignored my design rules and turned the system fan units uppside down so
instead of wenting hot air out it pressed hot air into the cabinet!!..
And yes he lost his job later and i was a bit happier! :-)
>Leaving out the caps can lead to EMI issue, e.g. short low-voltage bursts at
>neighboured gates which affect the functional behaviour, or emitted signal
>noise on analog circuits.
I think you mix EMI with RFI!
>That impedances resonance frequencies between the gates and wires can
>also play a role, was new to me it sounds disastrous, but I have to read
>some literature before I can give a statement on this.
It is disastrous, its a complex area to read about, still you wont get all the
ansvers by reading. Its about rise and fall times, impedance planes in PCB,
impedance and inductances in cabels, its really old stuff really.
>Are you sure that this is not an issue of HF logic and or high power designs only?
For some time now im been designing with the MSP430 MCU, its 8Mhz and
extreamly low power device, we are talking micro amp a full speed, still you
can get very strange behaviour if you do not decouple the device right, and
particularely if onedont decouple the internal 12 bit AD converter and its
reference. What tells this us? It tells us that “any design” of any speed or
power consumption can behave erratic due to bypass and power supply
issues.
For instance you have to bypass a “10khz Bw OP amp” properly otherwhise
it might become unstable, will ring, or even oscillate, it can state latch and
burn up, phase reverse, etc ,etc ,all at 10Khz!! Some of this dont even show
up in the data sheets!!
>Ok, I also have to say that at the beginning where I defined the MBHP
>my focus was on digital data processing, where signal noise doesn’t
>hurt so much like on mixed signal designs, so long frequencies are relatively
>low (< 50 MHz) and the TTL levels are stable.
Once again, its not a matter of speed, its about rise and fall times of gates
switching around. For instance you can a have a 1Mhz CLK and 10nS rise
and fall times,see!
>Using analog circuits (like the SID, AOUT, OPL3) was a new field which came
>later, and which was not taken into account from the beginning. Not sure how
>the MBHP would look today if it would be designed from scratch.
>As Duggle mentioned: it makes sense to consider such things on future designs.
Sorry but Duggle are on the wrong track!
Proper design starts at design start not after!
Just because that the project has been lucky so far is just because it
has been “lucky”,nothing else. Tomorrow when the code might have
changed, you might have a errendous working MBHP.
There is a saying for that:
Why make something simple, when you can make it difficult!
Design by chance is not design, its chancing!
Its like saying:
-:, well i design this 68HC12 system( who draws 50mA) with a 10mA power supply!!
In the software industry its a well known fact that a code change can
make a produkt go completely bananas! Se my story about the DSP!
Why! Because the new code flipps the gate in a different pattern,
and that pattern migh be in resonance with PCB tracks, cabels,
drivers, etc.
Here is another example story!
I designed once a ASIC emulator using virtex FPGA’s not one but
many in a large system, i turned bananas because i could not
callculate the power consumption of the system and therefore
designing the power supply become very problematic, the cause
was the ASIC engineers could not( or didnt want to tell, who knows)
estimate the FPGA’s gate switching pattern sequence, and that tells
the system designer if the FPGA will draw copius with power or a
moderate amount.
>However, if somebody thinks that he can reduce jitter on the analog inputs
>or background noise on the SID by following this suggestion, then add
>10nF or 100nF caps at the \Vss/Vdd pins of each IC from the bottom +
>one 10 uF per module (or 100 uF for modules with high current consumption
>like mentioned above), but from my experience it won’t solve the problems.
>Perhaps you will notice absolutely no difference - bypass caps cannot
>reduce glitches and spikes.
Why do you think engineers places 10-100nF ceramic or polyfim caps
between +pin at IC and gnd? For sheare fun? Because they like to waste
money?
>and they also don’t help to eliminate ground loops and all those disturbing factors.
I havent said anything about ground loops, but now i will, ground lops depends
on (among many)power planes with varying impedance, this leads to potential
difference wich in turn leads to “current flows”.
>Maybe I should also mention that I don’t hear any additional noise frm the
> SID when all 99 LEDs of the control surface are toggled with different frequencies.
<Why? Because the SID power lines are wired starlike from the PSU. Seems that this
>was sufficient. However…
Exactly,you have learned something here by experience, you wired them star like
wich means that you have removed some of the impedance dependancies to a
“”“lowimpedance”" summing juction at the power PCB.
Just because you tried a problem sugestion out of the skool book does’nt
mean that you actually understand what you did and what actuall happend
and thats the beauty of electronic design, to understand what you did
and what effect it had. And that takes years to learn.
>Karl, I must say that I’m happy about your posting. It’s an important reminder
>(I swear that the next MBHP modules will be littered with bypass caps in future 
>and contains some interesting informations about pot wiring, 4051 muxing, sockets too
At synth diy archives you can find a welth of info about decoupling, why
not use socketing , and impedances etc, also if you want to learn about
high speed (wich means rise and fall times) you ought to look at
Jack Gnassles web pages but most important read the book,
"“Black magic of high speed design” this is a industry bible! Beware!
>Sidenote: the jitter monitor application from the MIOS download page
>demonstrates that caps against ground or shielded cables won’t improve
>the signal quality here
I didnt talk about signal quailty, thats a completely different aspect,
im talking entierly about " system stability", you can have a stable
system but crap sound, and a unstable system with god sound.
I know, I have done both!
Just because a system works dosent mean it works god!
Windows anywone!
> maybe because of the reduced ADC resolution
>of 10bit. The jitter is normaly 1 bit, and this is caused by the 1/2 LSB error
>which can be found on any ADC. Sometimes I think that people are just too
>afraid that they are doing something wrong when they are “violating” such
>rules which are common in other design areas.
Just becuase it works on the PIC18F doesnt mean it will have the same
result in other MCUs, even a similare application with the same PIC18F
can give you very different results, you can even have different results
from different silicon batches from the same factory.
>This comment should not decrade your input!
Please everyone, understand this:
Im not trying to be nasty or the general wise guy, nor to tap you or
anyone down, i just point out a design error based on 20 years of
design experience. Im just trying to improve the MBHP design
for everyones happiness. If some folks feel embarrased or feeling
hurt, im sorry, but i cant do else!
Torsten you are a splendid software writer many more times
better then i will ever be, no question about that, but you and others
still have a lot to learn in hardware design. Im sorry to say but thats
the direction of the floating boat today!
There is simply no short cuts to take!
Best regards and intentions.
KD
