My initial problem was being unable to access the CV configuration menu, menu pages are just something I can’t find information on how to access all. So I made a shortcut to CVCFG in the mbseq_hw.v4 file, replacing SYSEX for now,
I have a green light on in the Aout_NG module, after doing the setup for Aout_NG.
My new problem in CV configuration is obtaining 5v for note C3, I can only adjust to a low of 8.4v. I’m using +/- 15v. power supply, that should be OK, so now I’m searching for the problem.
Now for my main problem, no CV and CV gates on Doutx4. Should the file “MBSEQ_CV.V4 file” be on my SD card if I have made the configurations properly, because I don’t see it there.
I have set the CV module to Aout_NG, set the OUT in Menu/Event to Aout and set the CV_GATE_SR1 to 3 in the MBSEQ_HW.V4 file. I think this is all the setup I need.
Also should J5A/B/C be enabled it is in my config by default
This is a typo, the AOUT interface should be in MBSEQ_GC.V4 (and not MBSEQ_CV.V4) file. However, you don’t edit this file directly, instead this file just stores the values that you changed in the CV configuration page.
Gates are configured in MBSEQ_HW.V4
You’ve to ensure that the 3rd SR isn’t assigned to any other function which could overlay the gate.
Typical errors if the CV interface isn’t working:
no proper connection via J19, e.g. swapped signal lines
too long cable between core and AOUT(_NG) module (max. 20 cm)
Most simple way to check the communication between core and AOUT_NG:
Enter the CV configuration page, select the right module (AOUT_NG), set Calibr.(ation) value to 1V, 2V, 4V, 8V
You should notice that the selected CV output should change it’s voltage.
If this works, you know that the MIDI track configuration doesn’t select the right AOUT port and channel.
Most simple way to check if gates are working:
Set “J5_ENABLED 1” in the MBSEQ_HW.V4 file, and connect a LED via 220 Ohm resistor between Vs (GND) and J5A.A0 to check if the gate is working with this pin.
If yes, do the same with the SR that you selected with CV_GATE_SR1
Note that the first gate is located at D7 (not D0) output pin!
If this test isn’t working, then your MIDI track configuration doesn’t select the right AOUT port and channel.
Fixed the CV gates problem, noob error, I was checking D0 for Ch1 gate when in fact it appears on D7 of J3 on the Dout module, so this verifies the Line Drivers are working OK.
It looks to me like there is no activity on J19 from the core board. On pins 9 + 15 of IC1 on the line driver transmitter board I have clock type activity on the scope, on the same pins on IC 2 (associated with J19) I have nothing. I’ve checked the solder connections on the core board so now I’m looking for a 74HCT541 to swap into IC1 on the core board.
Can you be more specific where the non-standard pinning occurs? is it core J19 <—>J19 transmitter board or J1 Aout_NG to receiver board or both? Does anyone have a graphic of the correct pinning?
Easiest way to do it quick. Here the black wire is pin 1, brown is pin 5 6 but the right-most. This cable is 1:1 on the Core, probably simplest to wire the line driver straight and yoga after. The top row relative to the guide nub contains the serial output (SO) and so should connect to the AOUT data header.
Can anyone help with the wiring from core J19 to J1 on the Aout_NG PCB? Does it wire up to the S0 row or the S1 row of J19?
I’d like to try that first before I wire J1 to the receiver module. I have a new IC1 in place on the core, I’m going to see if I can get J19 on the core talking to the Aout_NG module this a weekend.
You want to wire SO (serial output) from the Core to SI (serial input) on the AOUT_NG.
The top row of J19 is:
Vs Vd SO SC RC1
0V, 5V, serial out, serial clock, chip select 1.
J1 on AOUT_NG is:
Vs Vd CS SI SC
0V, 5V, chip select, serial input, serial clock.
You can see how the chip select jumps into the middle and pushes SI and SC over. So wiring up an IDC like I showed is one way around this mismatch. You could still use this cable with the line driver board ignoring the JAOUT header.
So this is what I learned from Latigid On’s post and how I wired it. I confirmed it with the wiring in tutorial 016 for the Aout configuration:
Common AOUT modules are connected to J19 of the MBHP_CORE_STM32 module:
J19:Vs -> AOUT Vs ``
J19:Vd -> AOUT Vd
J19:SO -> ``AOUT SI
J19:SC -> AOUT SC
J19:RC1 -> AOUT CS
Still does not work. I am getting CV gates, clocks, and triggers over the line drivers from the Dout SR's but no CV from the Aout_NG. I have tried at the core on J19 and over the line drivers and nothing, just 10v or so from the outputs. The lack of system clock at J19 makes me think this is a configuration issue, but i have CV gates. There is no SC at pin PB3 on the Discovery board.
The REF output might be interesting as well, it should output 2V once the TLB5630 has been correctly configured.
You can re-configure the device in the MBSEQ CV Configuration page during runtime (w/o power-cycling the core) by selecting a different interface, and then AOUT_NG again.
Last but not least: I just noticed that there is an integrated AOUT troubleshooting app in the MBSEQ firmware, which might help as well!
Enter “testaoutpin” in MIOS Terminal to get the appr. help page
The voltage does not change at any of these pins on the TLV5630, I’ve tried running the seq and adjusting the calibration control in CV Configuration while monitoring.
Values I get are
12. 4.20v
13. 4.20v
14. 4.20v
15 4.20v
6. .17v
7. .32v
8. 4.20v
9. 4.20v
Ref (Pin 16) is at .02v
I can toggle the three pins CS, SC, Si at core J19 using MIOS terminal and get 0v and 4.6v on each with testaoutpin 0 and 1
I also tried a LPC17 core using a new SD card and config with the same results and no Aout_NG action
I’m lost, usually things go very smooth with Midibox stuff
Could you please check with the “testaoutpin” command if the control signals also go to the DIN/SCLK/FS pin of the TLV5630? (pin 2/3/4) - if this is the case, the problem must be on the AOUT_NG board. Check all supply pins (GND and VDD pins), something seems to be wrong there.
If still no luck, we can’t exclude that the chip is defective.
