AIN handling from 2x core8 to core32

Design Concepts
1

hello,

I use 2 AINx4 on one core8 and 1 AINx4 on the other one.

Now, with core32, I know I’ll use my 3 AINx4 in a same chain.

I wrote “I know”, but it is more an “I guess”

I’m a bit confused with the hardware and software part

actually, I have 3 pins + 2x5 for each SR chains.

with core32, what is the best architecture I can build?

I mean, I have at least 2 options :

  • 2 AINx4 on one core32 port and the last one on another port.

  • the 3 AINx4 chained and this chain on only one core32 port

all infos would be appreciated :slight_smile:

all the best,

2

AINx4 modules are not chained, the three multiplexer control lines (J6:A/B/C) are connected in parallel - it’s really straightforward.

Best Regards, Thorsten.

3

ok Thorsten. I understand.

you meant J5:A/B/C …? I guess

in http://svnmios.midib…mios32_config.h (the 12th tutorial about AIN muxing), I found :

// control pins to select the muxed channel

#define MIOS32_AIN_MUX0_PIN GPIO_Pin_4 // J5C.A8

#define MIOS32_AIN_MUX0_PORT GPIOC

#define MIOS32_AIN_MUX1_PIN GPIO_Pin_5 // J5C.A9

#define MIOS32_AIN_MUX1_PORT GPIOC

#define MIOS32_AIN_MUX2_PIN GPIO_Pin_0 // J5C.A10

#define MIOS32_AIN_MUX2_PORT GPIOB

should I change something ?

I mean, I read in the readme file : the for MIOS8 compatible pin enumeration tip.

I’ll use it.

But should I define the MIOS32_AIN_MUX… constants ?

4

No, you were speaking of the MBHP_AIN module, therefore I referenced the three multiplexer control inputs at J6:A/B/C

The configuration has to be done in mios32_config.h as explained in the 012_ain_muxed tutorial example.

This would be a working configuration for up to 96 pots (control lines are connected to J19 instead of J5C, as you obviously want to use the analog inputs of J5C)

// AIN configuration:

// bit mask to enable channels
//
// Pin mapping on MBHP_CORE_STM32 module:
// 15 14 13 12 11 10 9 8
// J16.SO J16.SI J16.SC J16.RC J5C.A11 J5C.A10 J5C.A9 J5C.A8
// 7 6 5 4 3 2 1 0
// J5B.A7 J5B.A6 J5B.A5 J5B.A4 J5A.A3 J5A.A2 J5A.A1 J5A.A0
//
// Examples:
// mask 0x000f will enable all J5A channels
// mask 0x00f0 will enable all J5B channels
// mask 0x0f00 will enable all J5C channels
// mask 0x0fff will enable all J5A/B/C channels
// (all channels are disabled by default)
#define MIOS32_AIN_CHANNEL_MASK 0x0fff

// define the deadband (min. difference to report a change to the application hook)
// typically set to (2^(12-desired_resolution)-1)
// e.g. for a resolution of 7 bit, it's set to (2^(12-7)-1) = (2^5 - 1) = 31
#define MIOS32_AIN_DEADBAND 31


// muxed or unmuxed mode (0..3)?
// 0 == unmuxed mode
// 1 == 1 mux control line -> *2 channels
// 2 == 2 mux control line -> *4 channels
// 3 == 3 mux control line -> *8 channels
#define MIOS32_AIN_MUX_PINS 3

// control pins to select the muxed channel
#define MIOS32_AIN_MUX0_PIN GPIO_Pin_5 // J19.SO
#define MIOS32_AIN_MUX0_PORT GPIOB
#define MIOS32_AIN_MUX1_PIN GPIO_Pin_6 // J19.SC
#define MIOS32_AIN_MUX1_PORT GPIOB
#define MIOS32_AIN_MUX2_PIN GPIO_Pin_13 // J19.RC1
#define MIOS32_AIN_MUX2_PORT GPIOC
[/code]









Best Regards, Thorsten.
5

ok thorsten.

I guess I understood.

each AINx4 on J5:a, b & c.

the input control on J19:SO,SI & RC1

each AINx4 received the 3 input control on A, B & C I guess:

6

Yes, except for the connection name - you probably mixed it again.

The three control lines are located at MBHP_AIN::J6:A/B/C, they have to be connected to J19 in your special case (96 pot inputs)

The analog and supply lines are located at MBHP_AIN::J5, they have to be connected to MBHP_CORE_STM32::J5A/J5B/J5C

Best Regards Thorsten.

7

J19.SO

J19.SC

J19.RC1

are the correct name :slight_smile: (?!!)